1. Field of the Invention
The present invention relates generally to an electronic memory device. More particularly, the invention relates to a non-volatile memory device and a method of programming the same.
2. Description of the Related Art
Semiconductor memories are an essential part of most modern electronic systems such as computers and other digital logic platforms. Unfortunately, however, the performance of the electronic systems is often limited by the speed and the capacity of the semiconductor memories. In addition, the physical size of memory chips often places a restriction on the amount of miniaturization that can take place in the electronic systems. Because of the limiting effect that semiconductor memories have on modern electronic systems, there is a continuing need to create faster, more highly integrated semiconductor memories. In order to do so, improvements need to be made to the manufacturing technologies used to create these memories. In particular, processing techniques for creating more densely integrated, higher frequency semiconductor memories need to be developed.
Semiconductor memory devices are generally grouped into two broad categories: volatile semiconductor memory devices and non-volatile semiconductor memory devices. Briefly, volatile semiconductor memory devices provide persistent data storage as long as power is supplied to the devices, but they lose the data once the power is cut off. Non-volatile semiconductor memory devices, on the other hand, provide persistent data storage even when power to the devices is cut off or suspended.
Because of their ability to provide persistent data storage even when power is cut off, non-volatile memory devices are commonly used to provide long term storage for data such as program files and microcode. Non-volatile memory devices are frequently used in application areas such as personal computers, aerospace electronic engineering, communication systems, and consumer electronics.
Some non-volatile semiconductor memories are adapted for reprogramming and others are not. For example, due to design limitations, mask-programmed read-only memory (MROM) and programmable read-only memory (PROM) can be programmed only once during their lifetime. Erasable programmable read-only memory (EPROM) can be reprogrammed, but only after exposing it to ultraviolet light for several minutes to erase previously stored data. Electrically erasable programmable read-only memory (EEPROM), on the other hand, provides efficient reprogramming capability by allowing memory cells to be reprogrammed by simply applying electric fields to the cells. EEPROMs can generally be reprogrammed more than one hundred thousand times during their lifetime.
Flash memory is a special type of EEPROM in which multiple memory blocks are erased or programmed by a single programming operation. The performance of flash memory is generally superior to that of normal EEPROM, which only allows one memory block to be erased or programmed at a time. In addition, flash memory provides fast access times for read operations and is resistant to physical shock, thus making it an attractive option for high performance portable devices such as cellular phones and personal digital assistants (PDAs).
A typical flash memory comprises an array of transistors called cells, wherein each cell has a source and a drain formed on a substrate and two gate structures formed on the substrate between the source and the drain terminals. The two gate structures generally comprise a floating gate surrounded by an insulating layer and a control gate formed on the floating gate. The floating gate is used to store electrons determining a logic state for the cell.
A flash memory cell is read by placing a voltage on its control gate and detecting whether a current flows between its drain and source. Depending on how many electrons are stored in the floating gate, the voltage applied to the control gate will either allow current to flow between the drain and the source or it will not. For example, where a large number of electrons is stored in the floating gate, the electrons have a canceling effect on the voltage applied to the control gate, thereby affecting whether current flows between the drain and the source. In other words, the electrons stored in the floating gate modify the threshold voltage of the cell, i.e. the voltage that has to be applied to the control gate in order for current to flow between the drain and the source.
Due to variations in flash memory cells such as their geometry or a voltage used to program the memory cells, there tends to be variation in the threshold voltages of flash memory cells that have been programmed. Where the variation in the threshold voltages of the memory cells is not properly regulated, it can cause the flash memory to have poor performance.
In order to regulate a threshold voltage distribution for programmed memory cells, the memory cells are generally programmed using an incremental step pulse programming (ISPP) scheme such as that illustrated by FIG. 1. Referring to FIG. 1, a programming voltage VWL is applied to a wordline. Programming voltage VWL is increased in multiple program loop iterations executed during a programming operation. Each program loop comprises a programming period and a program verification period. In each program loop, programming voltage VWL is incremented by an amount ΔV. During the programming operation, a threshold voltage Vt of a cell being programmed increases by amount ΔV in each program loop. In order to minimize variation in the threshold voltage distribution, amount ΔV should be small. As increment ΔV becomes smaller, the number of program loops becomes larger. Since there is a tradeoff between the number of program loops required and the variance of the threshold voltage distribution, ΔV should be chosen to minimize the variance of the threshold voltage as much as possible without significantly limiting the performance of the memory device by requiring too many program loops.
A programming scheme for a non-volatile memory device using ISPP is disclosed, for example, in U.S. Pat. No. 6,266,270. Circuits for generating programming voltages using ISPP are disclosed, for example, in U.S. Pat. No. 5,642,309 and in Korean Patent Publication No. 2002-39744.
As described above, when programming a NOR flash memory device using an ISPP scheme, a wordline voltage (e.g., 3V to 10V, ΔV=0.3V) is applied to a control gate of a flash cell, a bitline voltage of about 5V-6V is applied to the drain of the flash cell and a voltage lower than 0 (e.g., −1V) is applied to a bulk or substrate of the flash cell. In general, a cell current Icell flowing through a memory cell is proportional to (VGS−Vt)2, where Vt is a threshold voltage of the memory cell and VGS is a gate to source voltage of the memory cell. The bitline voltage is generated and maintained by a charge pump (not shown). Where an amount of cell current flowing through the memory cell exceeds the capacity of the charge pump for the bitline voltage, the bitline voltage falls below a predetermined voltage level. As the bitline voltage (i.e. the drain voltage) is decreased, the threshold voltage of the flash cell fails to increase by a desired amount during a programming operation as indicated by a broken line in FIG. 1. In particular, as successive program loops are executed according to an ISPP scheme, a difference between the threshold voltage of the flash cell and the wordline voltage steadily increases. As a result, various characteristics of programmed cells are degraded, or programming failures may occur.
Similar to the bitline voltage, a bulk voltage is also generated and maintained by a charge pump (not shown). Where an amount of a cell current flowing through the memory cell exceeds an amount of a charge pump for the bulk voltage, the bulk voltage is increased above a predetermined voltage. As the bulk voltage increases above the predetermined voltage, the threshold voltage of the flash cell fails to increase by a desired amount during a programming operation as indicated by the broken line in FIG. 1. In particular, as successive program loops are executed according to an ISPP scheme, a difference between the threshold voltage of the flash cell and the wordline voltage steadily increases. As a result, various characteristics of programmed cells are degraded, and programming failures may occur.
Accordingly, a new approach capable of preventing programming failures caused by an increased bulk voltage or a decreases bitline voltage is desperately needed.